1. Field of Invention
The present invention relates generally to methods of fabricating integrated circuits. More particularly the use of Electron Cyclotron Resonance Chemical Vapor Deposition (ECR CVD) oxide films and optimized underlayer structures to maintain Chemical Mechanical Polishing (CMP) removal rates during fabrication is disclosed.
2. Description of the Prior Art
Maintaining the planarity of a semiconductor wafer surface during fabrication is crucial to ensure that there is no accidental coupling of active conductive traces between multiple active trace layers on integrated circuits housed on the wafer, and further to provide a surface with a constant height for any subsequent lithography processes. There are many processes which are intended to improve the planarity of a wafer surface during fabrication.
Chemical Mechanical Polishing (CMP) is one process which has been shown to have a high level of success in improving global, or long range, planarity. CMP has also been observed to improve the depth of focus margins for the lithography process. A typical CMP process involves the use of a polishing pad made from a synthetic material, such as polyurethane, and a polishing slurry which includes pH-balanced chemicals, such as sodium hydroxide, and silicon dioxide particles. Semiconductor wafers are mounted on a polishing fixture such that the wafers are held by a vacuum and pressed against the polishing pad under high pressure. The fixture then rotates and translates the wafers relative to the polishing pad. The polishing slurry assists in the actual polishing of the wafers. Ideally, the polishing pad has a rough surface, so the polishing slurry can flow between tiny crevices in the polishing pad and the surface of the wafer. While the pH of the polishing slurry controls the chemical reactions, e.g. the oxidation of the chemicals which comprise a passivation layer of the wafer, the size of the silicon dioxide particles controls the physical abrasion of surface of the wafer. The polishing of the wafer is accomplished when the silicon dioxide particles abrade away the oxidized chemicals.
Raised areas on the surface of a semiconductor wafer are the portions of the wafer which are polished during a CMP process. FIG. 1 is a diagrammatic illustration of the top view of a semiconductor wafer 10 which includes four integrated circuit chips 20. Each integrated circuit chip 20 has a plurality of active conductive traces 40 and is surrounded by a guard ring 30. The active conductive traces 40 are metal traces which are arranged to electrically couple associated elements of each integrated circuit 20. The active conductive traces 40, when covered with an insulating layer (not shown), form raised areas which make contact with a polishing pad. It should be appreciated that a typical integrated circuit includes a high density of active conductive traces. For illustrative purposes, the integrated circuit chips 20 shown in FIG. 1 have been simplified to include only a few active conductive traces 40. The guard rings 30 are typically metal lines which are formed around the perimeter of an integrated circuit. When an insulating layer (not shown) is deposited over the guard rings 30, raised areas are formed. Similarly, scribe lines 60, or lines on the surface of the semiconductor wafer 10 which mark the locations where the wafer 10 should eventually be cut to separate the integrated circuit chips 20, may also form raised areas when they are covered with an insulating layer (not shown).
In order for the CMP process to be consistent in planarizing the surface of a semiconductor wafer, the polishing pad used in the CMP process must be conditioned periodically. Conditioning allows polishing slurry to flow between the polishing pad and the surface of the wafer. The surface of the polishing pad needs to be mechanically abraded to maintain a consistent material removal rate during the CMP process. A polishing pad is conditioned by a conditioning disk, embedded with diamond tips, which is held down and rotated on the polishing pad which is being conditioned.
The use of diamond tips to condition the polishing pads used in the CMP process has been shown to be effective. However, conditioning a polishing pad after several wafers, i.e. one to ten, are polished is time consuming. The manufacturability of the CMP process would be improved with the development of a method which would reduce the frequency at which polishing pads must be conditioned.